JPS56121138A - Buffer memory controlling system - Google Patents

Buffer memory controlling system

Info

Publication number
JPS56121138A
JPS56121138A JP2436980A JP2436980A JPS56121138A JP S56121138 A JPS56121138 A JP S56121138A JP 2436980 A JP2436980 A JP 2436980A JP 2436980 A JP2436980 A JP 2436980A JP S56121138 A JPS56121138 A JP S56121138A
Authority
JP
Japan
Prior art keywords
data
idle
cell
queue
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2436980A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6138510B2 (en]
Inventor
Etsuo Masuda
Yukio Nakamura
Akihiko Doi
Hiroshi Fujita
Chikayoshi Hosokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2436980A priority Critical patent/JPS56121138A/ja
Publication of JPS56121138A publication Critical patent/JPS56121138A/ja
Publication of JPS6138510B2 publication Critical patent/JPS6138510B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
JP2436980A 1980-02-28 1980-02-28 Buffer memory controlling system Granted JPS56121138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2436980A JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2436980A JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Publications (2)

Publication Number Publication Date
JPS56121138A true JPS56121138A (en) 1981-09-22
JPS6138510B2 JPS6138510B2 (en]) 1986-08-29

Family

ID=12136268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2436980A Granted JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Country Status (1)

Country Link
JP (1) JPS56121138A (en])

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161038A (ja) * 1982-03-19 1983-09-24 Fujitsu Ltd バツフア管理方式
JPS6091482A (ja) * 1983-10-24 1985-05-22 Fujitsu Ltd メモリ管理方式
JPS61224593A (ja) * 1985-03-29 1986-10-06 Hitachi Ltd 加入者デ−タ制御方法
JPS6319939A (ja) * 1986-07-14 1988-01-27 Fujitsu Ltd 通信制御装置
US6411404B1 (en) 1993-11-10 2002-06-25 Matsushita Graphic Communication Systems, Inc. Memory management device and communication apparatus comprising said memory management device
JP2006526202A (ja) * 2003-05-12 2006-11-16 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピューティング環境のストレージをダイジェスト化するための方法、システム、およびコンピュータ・プログラム（メッセージ・ダイジェスト化命令の処理）
US7720220B2 (en) 2003-05-12 2010-05-18 International Business Machines Corporation Cipher message assist instruction
US7770024B2 (en) 2003-05-12 2010-08-03 International Business Machines Corporation Security message authentication instruction

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62182405U (en]) * 1986-05-09 1987-11-19

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161038A (ja) * 1982-03-19 1983-09-24 Fujitsu Ltd バツフア管理方式
JPS6091482A (ja) * 1983-10-24 1985-05-22 Fujitsu Ltd メモリ管理方式
JPS61224593A (ja) * 1985-03-29 1986-10-06 Hitachi Ltd 加入者デ−タ制御方法
JPS6319939A (ja) * 1986-07-14 1988-01-27 Fujitsu Ltd 通信制御装置
US6411404B1 (en) 1993-11-10 2002-06-25 Matsushita Graphic Communication Systems, Inc. Memory management device and communication apparatus comprising said memory management device
US6549297B1 (en) 1993-11-10 2003-04-15 Panasonic Communications Co., Ltd. Communication apparatus and speech message method
US7075675B2 (en) 1993-11-10 2006-07-11 Matsushita Electric Industrial Co., Ltd. Memory management apparatus and communication apparatus
JP2006526202A (ja) * 2003-05-12 2006-11-16 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピューティング環境のストレージをダイジェスト化するための方法、システム、およびコンピュータ・プログラム（メッセージ・ダイジェスト化命令の処理）
JP2007080278A (ja) * 2003-05-12 2007-03-29 Internatl Business Mach Corp <Ibm> 埋め込み符号を持ったコンピュータ命令値フィールド
US7720220B2 (en) 2003-05-12 2010-05-18 International Business Machines Corporation Cipher message assist instruction
US7725736B2 (en) 2003-05-12 2010-05-25 International Business Machines Corporation Message digest instruction
US7770024B2 (en) 2003-05-12 2010-08-03 International Business Machines Corporation Security message authentication instruction
JP4817189B2 (ja) * 2003-05-12 2011-11-16 インターナショナル・ビジネス・マシーンズ・コーポレーション メッセージ・ダイジェスト化命令を実行するための方法、システムおよびコンピュータ・プログラム
US8103860B2 (en) 2003-05-12 2012-01-24 International Business Machines Corporation Optional function multi-function instruction
US8661231B2 (en) 2003-05-12 2014-02-25 International Business Machines Corporation Multi-function instruction that determines whether functions are installed on a system
US9424055B2 (en) 2003-05-12 2016-08-23 International Business Machines Corporation Multi-function instruction that determines whether functions are installed on a system

Also Published As

Publication number Publication date
JPS6138510B2 (en]) 1986-08-29

Similar Documents

Publication Publication Date Title
JPS56121138A (en) Buffer memory controlling system
JPS56114063A (en) Multiprocessor
JPS57138220A (en) Data input equipment for logical circuit
JPS55103656A (en) Information processing system
JPS57157325A (en) Microcomputer
JPS56124930A (en) Initial program loader system
EP0230721A3 (en) Multiprocessor control system
JPS56135266A (en) Data processing system
JPS57134704A (en) Programmable logical controller
JPS5523510A (en) Sequence control unit
JPS54114945A (en) Information processing system
JPS5616221A (en) Control system for data transfer
JPS5798030A (en) Data processing system
JPS56121168A (en) Common resource control system of multiple central processing unit system etc
JPS57212517A (en) Operation status changing system of computer
JPS5482946A (en) Duplex system of sequence controller
JPS5537644A (en) Input-output circuit of microcomputer
JPS54115036A (en) Control system for microprogram
JPS5779504A (en) Controlling method of parallel processing type programmable controller
JPS6465653A (en) Communication control system
JPS56127233A (en) Input/output control system
JPS5532180A (en) Sequence controller capable of connecting plurality of external equipments
JPS57157330A (en) Input and output control system
JPS56137454A (en) Computer system for process control
JPS54156444A (en) Processing system for input and output instruction